ASIC and FPGA Verification

Digital electronic designs continue to evolve toward more complex, higher pincount components operating at higher clock frequencies. This makes debugging board designs in a lab considerably more difficult. At the same time, the interfaces to standard components on the board are often not verified until a prototype is built. While engineers agree that fixing problems at that stage in the design process is too expensive, they have not performed up-front board-level simulation because they lack models and a methodology for doing so. This book specifically addresses both these issues. Rick Munden details the creation and use of models designed to verify ASIC and FPGA designs as well as board-level designs that use off-the-shelf digital components. The models are based on the VHDL/VITAL standard.